1. Field of the Invention
This invention generally relates to serial bit receivers and, more particularly, to a system and method for using a half-rate clock phase detector to receive serial data and generate a data clock.
2. Description of the Related Art
In clock and data recovery (CDR) circuits, phase-locked loops (PLLs) are essential in recovering the received data clock, as well as retiming the data. Hogge phase detectors, or Hogge detector variants are often used for this purpose because of their simplicity and linear behavior. However, at very high data rates the pulse widths can become so narrow that cannot be handled properly by Hogge phase detector. Alternately stated, the propagation delays become larger than the pulse widths. Potential phase detection consequences include no zero-crossing, data pattern dependent zero-crossings offsets, or phase-voltage transfer curves with very narrow linear ranges.
FIG. 1 is a schematic diagram of a simplified half-rate Hogge phase detector (prior art). The circuit consists of four latches, L1 to L4, forming two sets of flip-flops and two XOR gates, X1 and X2. For illustration purpose, all signal paths are shown single-ended (unbalanced). However, many applications use a differential implementation. The data is input to latches L1 and L2, and then retimed to output demultiplexed data Q1 and Q2. Those two flip-flops are driven by half-rate clocks CLK and CLKB, respectively. To provide phase and reference signals to a loop filter (not shown), that eventually controls a voltage controlled oscillator VCO (not shown), an exclusive-OR (XOR) operation is performed on output signals Q1 and Q2, Q3 and Q4 to obtain phase and reference signals.
FIG. 2 is a timing diagram associated with the operation of the Hogge detector in FIG. 1 (prior art). When the VCO is locked, the phase signal pulses are only half as wide as the reference signal pulses. When locked, pulse width of Q1 and Q2 can only be half the period of the full-rate clock. At high data rates it may be difficult for the latches to output short pulses with full voltage swings. When relatively wide linear region of phase-voltage transfer curve are required, latches L1 and L2 must provide even shorter pulses. However, XOR gate X1 may be unable to handle especially short pulse widths.
These short pulses can cause a variety of problems. If the latches cannot generate pulse as wide as the width of half period full-rate clock, the loop phase detector (not shown) may have no zero crossing in its phase-voltage transfer curve. If latches can output such short pulses, but cannot reach full swing, then data pattern dependent zero-crossing offsets will occur. For example, the swing for a “1100” data pattern might be better than for a “1010” pattern. If latches can output short pulses with a full swing, but cannot output even shorter pulses, then the linear region of phase-voltage transfer curve may become too narrow. Therefore, performance of the phase detector is heavily dependent upon the latch performance.
It would be advantageous if the latches in a Hogge detector could be made to operate at a lower speed while supporting higher phase detector data rates.